Level converter provided with slew-rate controlling means

ABSTRACT

A level converter for the converting of a first digital signal (U 1 ) having a first voltage range into a second digital signal (U 2 ) having a second voltage range comprising an amplifier (T 0 ) having an input for receiving the first digital signal (U 1 ) and an output for supplying the second digital signal (U 2 ), a series arrangement for controlling the slew-rate of the second digital signal (U 2 ) which comprises at least a first capacitor (C 1 ) and a second capacitor (C 2 ) and which is coupled between the output and the input of the amplifier (T 0 ), and voltage controlling means for controlling the voltages (V C1 , V C2 ) across the at least first and second capacitors (C 1 , C 2 ). The voltage controlling means comprises at least one voltage source (V ls1 , V ls2 ) for supplying a separate bias voltage to each internal node (N 1 , N 2 ) of the series arrangement. The value of the separate bias voltage or the values of the separate bias voltages is/are dependent on the values of the first (U 1 ) and the second (U 2 ) digital signals.

The invention relates to a level converter for the converting of a firstdigital signal having a first voltage range into a second digital signalhaving a second voltage range comprising an amplifier having an inputfor receiving the first digital signal and an output for supplying thesecond digital signal, a series arrangement for controlling theslew-rate of the second digital signal which comprises at least a firstcapacitor and a second capacitor and which is coupled between the outputand the input of the amplifier, and voltage controlling means forcontrolling the voltages across the at least first and secondcapacitors.

Such a level converter is known from the general state of the art asshown in FIG. 1. It must be stated that where the wordings “level of asignal” is used, the word “level” has to be interpreted as the maximumpossible voltage value of the signal minus the minimum possible voltagevalue of the signal. (The minimum possible voltage level is usual closeto zero volt.) The known level converter comprises a field effecttransistor T₀ having a gate for receiving a first digital signal U₁, asource connected to a supply reference terminal GND and a drainconnected to an output terminal 2 for delivering a second digital signalU₂. The output terminal 2 is connected, via a load Z_(L), to a supplyvoltage supplied by a supply voltage source SPL_(LV) of the levelconverter. The load Z_(L) may also be replaced by various kinds ofcircuitries for example by a current source. A series arrangement of afirst and a second capacitor C₁, C₂ is connected between the drain andthe gate of the field effect transistor T₀. The first and the secondcapacitors C₁, C₂ are respectively shunted by a first and a second shuntresistor R₁, R₂. The known level converter further comprises a pré-drivecircuit PDC having a first supply reference connected to the supplyreference terminal GND, a second supply reference connected, via aseries resistor R_(PDC), to a pré-drive supply voltage source SPL_(PDC),an input coupled to an input terminal 1 of the level converter, and anoutput coupled to the gate of the field effect transistor T₀.

The principle operation of the known level converter is as follows. Theinput 1 is connected to any digital circuit which supplies a digitalsignal of which the voltage level must be adapted, normally to a highervoltage level. This digital signal is buffered by the pré-drive circuitPDC which delivers a first digital signal U₁, of the level converter.The level of the first digital signal U₁ is determined by the value ofthe supply voltage supplied by the pré-drive supply voltage sourceSPL_(PDC). The field effect transistor T₀ in conjunction with the loadZ_(L) converts the first digital signal U₁ into the second digitalsignal U₂. The level of the second digital signal U₂ is determined bythe value of the supply voltage supplied by the supply voltage sourceSPL_(LV) of the level converter.

Many known level converters have the disadvantage that they causeelectromagnetic interference and/or groundbounce in other digitalcircuits, if applied in an integrated circuit. This has been solved in away as in the known level converter as shown in FIG. 1. In fact twomeasures are normally implemented. The first measure is the applicationof the series resistor R_(PDC) for limiting the current which can besupplied by the output of the pré-drive circuit PDC. The second measureis the application of a capacitive path connected between the drain andthe gate of the field effect transistor T₀. By so doing the slew-rate ofthe second digital signal U₂ is controlled and is approximately equal tothe quotient of the value of the limited current and the value of thecapacitance formed by the capacitive path. The application of the seriesresistor R_(PDC) is optional because the current is also limited by thepré-drive circuit itself. However if the series resistor R_(PDC) isomitted the value of the limited current can generally not be predictedvery accurately. The simplest implementation for the capacitive pathwould be a single capacitor connected between the drain and the gate ofthe field effect transistor T₀. However if applied in an integratedcircuit this can lead to the problem that the voltage across the singlecapacitor is higher than permitted. In the known level converter asshown in FIG. 1 this problem is solved by forming the capacitive path bya series arrangement of a first and a second capacitor C₁, C₂. Since thecommon node of the first and the second capacitor may not be aDC-floating node the first and the second capacitor C₁, C₂ are shuntedrespectively by the first and the second shunt resistor R₁, R₂.

A problem of the known level converter is that the shunt resistors R₁and R₂ increase the static power dissipation of the level converter.

It is an object of the invention to provide a level converter which hasa reduced static power dissipation.

To this end, according to the invention, the level converter of the typedefined in the opening paragraph is characterized in that the voltagecontrolling means comprises at least one voltage source for supplying aseparate bias voltage to each internal node of the series arrangement,and in that the value of the separate bias voltage or the values of theseparate bias voltages is/are dependent on the values of the first andthe second digital signals.

The invention is based on the insight that in the known level converteras shown in FIG. 1 the increase of the static power dissipation iscaused by the fact that the first and the second resistors form togethera DC-path between the drain and the gate of the field effect transistorT₀. In principle this is not necessary. Only the internal node(s) (InFIG. 1 there is only one internal node N₁) must be biased becauseotherwise the/these internal node(s) would be DC-floating nodes. Forclarity it is stated that the outer nodes of the series arrangement forcontrolling the slew-rate of the second digital signal U₂ may not beinterpreted as internal nodes of said series arrangement.

When the state of the first and second digital signal changes, thevoltage on the internal nodes have to be changed as well. In the knownlevel converter this occurs automatically by the fact that the seriesarrangement of the first and the second resistors form a voltagedivider. Since a level converter according to the invention do not havesuch a voltage divider the voltages on the internal nodes must beadapted in a different way. For this reason the at least one voltagesource for supplying the bias voltage to the internal node or forsupplying separate bias voltages to each internal node must be madedependent on the values of the first and the second digital signals.

An embodiment of the invention may be characterized in that a biasresistor is arranged in series with at least one of the at least onevoltages sources. If the aforementioned dependency of the at least onevoltage source is not optimal (which in practice is nearly always thecase) then the dynamic power dissipation of the level converter will beincreased. This increase of the dynamic power dissipation is reduced bythe application of a bias resistor to each internal node of the seriesarrangement for controlling the slew-rate of the second digital signalU₂. The value of the bias resistors can however not be chosenarbitrarily high because a too high value of the bias resistor willcause a too inaccurate control of the voltages of the internal nodes. Itmay not always be necessary to physically implement the bias resistorsbecause the internal resistances of the voltage source or sources forsupplying the bias voltage or voltages to each internal node may wellserve as said bias resistors.

A further embodiment of the invention may be characterized in thatswitching means is/are arranged in series with the at least one voltagessources. By so doing a type of class C biasing of each internal node canbe accomplished by a proper functioning of said switches, that is to saythat a respective switch is opened (non-conducting) as long as thecorresponding internal node to which it is coupled is within a certainvoltage. As a consequence no charging or discharging occurs as long asthe voltage at the corresponding internal node is within said voltagerange. This has the advantage that the dynamic power dissipation of thelevel converter is reduced even in the case that the (separate) biasvoltages delivered by the voltage sources are not so very accurate.

A further embodiment of the invention may be characterized in that theswitching means is formed by diodes. By this a very simpleimplementation for the aforementioned switches is accomplished.

Further advantageous embodiments of the invention are specified inclaims 5 and 6.

The invention will be described in more detail with reference to theaccompanying drawings, in which:

FIG. 1 is a circuit diagram of a known level converter;

FIG. 2 is a circuit diagram of a first embodiment of a level converteraccording to the invention;

FIG. 3 is a circuit diagram of a second embodiment of a level converteraccording to the invention;

FIG. 4 is a circuit diagram of a third embodiment of a level converteraccording to the invention; and

FIG. 5 is a set of signal diagrams I-VII for further explaining theembodiments of FIG. 2.

In these Figures parts or elements having like functions or purposesbear the same reference symbols.

FIG. 2 shows a circuit diagram of a first embodiment of a levelconverter according to the invention. The level converter comprises afield effect transistor T₀ having a gate for receiving a first digitalsignal U₁, a source connected to a supply reference terminal GND and adrain connected to an output terminal 2 of the level converter fordelivering a second digital signal U₂. The output terminal 2 isconnected, via a load Z_(L), to a supply voltage supplied by a supplyvoltage source SPL_(LV) of the level converter. The load Z_(L) may alsobe replaced by various kinds of circuitries for example by a currentsource. A series arrangement of a first and a second capacitor C₁, C₂ isconnected between the drain and the gate of the field effect transistorT₀. The level converter further comprises a pré-drive circuit PDC havinga first supply reference connected to the supply reference terminal GND,a second supply reference connected, via a series resistor R_(PDC), to apré-drive supply voltage source SPL_(PDC), an input coupled to an inputterminal 1 of the level converter, and an output coupled to the gate ofthe field effect transistor T₀. The level converter further comprises avoltage source V_(ls1) which is connected between the output terminal 2and, via a bias resistor RB, to the internal node N₁ of the seriesarrangement of the first and the second capacitor C₁, C₂.

The principle operation of the level converter is as follows. The input1 is connected to any digital circuit which supplies a digital signal V₁of which the voltage level must be adapted, normally to a higher voltagelevel. This digital signal V₁ is buffered by the pré-drive circuit PDCwhich delivers a first digital signal U₁ of the level converter. Thelevel of the first digital signal U₁ is determined by the value of thesupply voltage supplied by the pré-drive supply voltage sourceSPL_(PDC). The field effect transistor T₀ in conjunction with the loadZ_(L) converts the first digital signal U₁ into the second digitalsignal U₂. The level of the second digital signal U₂ is determined bythe value of the supply voltage supplied by the supply voltage sourceSPL_(LV) of the level converter. The series resistor R_(PDC) limits thecurrent which can be supplied by the output of the pré-drive circuitPDC. The slew-rate of the second digital signal U₂ is approximatelyequal to the quotient of the value of the limited current and the valueof the capacitance formed by the series arrangement of the first and thesecond capacitor C₁, C₂.

The operation of the level converter according to FIG. 2 is furtherexplained in conjunction with the signal diagrams I-VII as shown in FIG.5. As an example it is assumed that the capacitance of the firstcapacitor C₁ is equal to the capacitance of the second capacitor C₂. Itis further, by way of an example, assumed that the level of the firstdigital signal U₁ equals 2.5 Volt and that the level of the seconddigital signal U₂ equals 5.0 Volt. In this situation the optimaldependency of the bias voltage V_(ls1) is as shown in diagrams II, III,and VII. In order to better explain the operation of the circuitaccording to FIG. 2 one has first to consider the following theoreticalsituation: the internal node N₁ is a DC-floating node, the first and thesecond capacitors C₁ and C₂ are ideal capacitors and are not charged, V₁equals 0 Volt, U₁ equals 0 Volt, and U₂ equals 5.0 volt. At time t₁ V₁changes from 0 Volt to 2.5 Volt. As a consequence U₁ changes from 0 Voltto 2.5 Volt and U₂ changes from 5.0 Volt to 0 Volt. The voltage U_(C1)across the first capacitor C₁, the voltage U₂ across the secondcapacitor C₂, and the voltage U_(N1) at the internal node N₁ aredirectly (Kirchhoff's law) determined from the signals U₁, and U₂, andare as shown in diagrams IV, V, and VI. If now the practical situationis considered that the first and second capacitors C₁ and C₂ are notideal and are burdened with parasitic DC-leakage paths, it is clear thatthe voltages U_(C1), U₂, and U_(N1) may deviate from the ideal situationas indicated in the diagrams IV, V, and VI. In order to avoid thisproblem the internal node N₁ is DC-biased by the series arrangement ofthe bias resistor RB and the voltage source V_(ls1). By so doing thestatic power dissipation of the level converter is hardly increasedsince the parasitic DC-leakage paths of the first and the secondcapacitors are virtually infinite and thus there is no significantDC-path between the drain and the gate of the field effect transistorT₀. However in order to avoid a significant increase in dynamic powerdissipation the voltage V_(ls1), as indicated in diagram VII, must beabout equal to the ideal voltage U_(C1) as indicated in diagram IVbecause then the (dynamic) current through the bias resistor RB isnegligible. For this reason the accuracy of the bias voltage V_(ls1)must be relatively high.

FIG. 3 shows a circuit diagram of a second embodiment of a levelconverter according to the invention. A difference of the embodiment ofFIG. 3 compared to FIG. 2 is that the bias resistor RB is replaced by afirst diode D₁. Another difference is that a series arrangement of asecond voltage source V_(ls2) and a second diode D₂ is arranged inparallel of the series arrangement of the first voltage source V_(ls1)(formerly denoted as voltage source V_(ls1)) and the first diode D₁. Yetanother difference is that the first bias voltage V_(ls1) is yet notsignal dependent by has a constant DC-value. The second bias voltageV_(ls2) is also not signal dependent but has a constant DC-value whichis normally different from the constant DC-value of the first biasvoltage V_(ls1). The first and second diodes D₁ and D₂ are in factswitches which automatically select either the first voltage sourceV_(ls1) to be coupled to the internal node N₁ or the second voltagesource V_(ls2) to be coupled to the internal node N₁. By so doing thefunction of a single but signal dependent voltage source V_(ls1), (seeFIG. 5, diagram VII) is more easily implemented by the first voltagesource V_(ls2), the second voltage source V_(ls2), the first diode D₁and the second diode D₂. Further more by the application of the firstand the second diodes D₁ and D₂ a certain voltage range around thedesired voltage of the internal node N₁ is created. As a consequence nocharging or discharging of the first and the second capacitors occurs aslong as the voltage at the internal node N₁ is within said voltagerange. This has the advantage that the dynamic power dissipation of thelevel converter is reduced even in the case that the separate biasvoltages V_(ls1), and V_(ls2) delivered respectively by the first andsecond voltage sources V_(ls1) and V_(ls2) are not so very accurate. Ifby way of example it is assumed that the capacitances of the first andthe second capacitors C₁ and C₂ are equal, the level of the firstdigital signal U₁ equals 2.5 Volt, the level of the second digitalsignal U₂ equals 2.5Volt, and that the threshold voltage of the firstand second diodes are 0.5 Volt, then appropriate constant DC-values forV_(ls1) and V_(ls2) are respectively +1.75 Volt and −1.0 Volt.

FIG. 4 shows a circuit diagram of a third embodiment of a levelconverter according to the invention.

A difference compared to the second embodiment is that the seriesarrangement for controlling the slew-rate of the second digital signalU₂ comprises a first capacitor C₁, a second capacitor C₂, and a thirdcapacitor C₃. As a consequence the said series arrangement comprises twointernal nodes: a first internal node N₁ and a second internal node N₂.

The voltage controlling means comprises first until seventh N-type fieldeffect transistors T₁-T₇ and eighth until eleventh P-type field effecttransistors T₈-T ₁₁. The first field effect transistor T₁ comprises asource connected to the common node N₁ of the first capacitor C₁ and thesecond capacitor C₂, a drain connected to the drain D of the transistorT₀, and a gate. The second field effect transistor T₂ comprises a sourceconnected to the gate of the first field effect transistor T₁, and adrain and a gate which are both connected to the source of the firstfield effect transistor T₁. The third field effect transistor T₃comprises a source, a drain connected to the drain D of the transistorT₀, and a gate. The fourth field effect transistor T₄ comprises a sourceconnected to the gate of the first field effect transistor T₁, a drainconnected tot the source of the third field effect transistor T₃, and agate. The fifth field effect transistor T₅ comprises a source connectedto the common node N₂ of the second capacitor C₂ and the third capacitorC₃, a drain connected to the source of the first field effect transistorT₁, and a gate. The sixth field effect transistor T₆ comprises a sourceconnected to a bias reference terminal BIAS for receiving a bias voltageV_(BIAS), and a drain and a gate which are both connected to the sourceof the fifth transistor T₅. The seventh field effect transistor T₇comprises a source connected to the gate of the fifth field effecttransistor T₅, a drain connected to the source of the fourth fieldeffect transistor T₄, and a gate connected to the bias referenceterminal BIAS. The eighth field effect transistor T₈ comprises a sourceconnected to the gate of the third field effect transistor T₃, a drainconnected to the drain of the transistor T₀, and a gate. The ninth fieldeffect transistor T₉ comprises a source connected to the gate of thethird field effect transistor T₃, a drain connected to the gate of theeight field effect transistor T₈, and a gate connected to the drain ofthe transistor T₀. The tenth field effect transistor T₁₀ comprises asource connected to the gate of the fourth field effect transistor T₄and to the gate of the eight field effect transistor T₈, a drainconnected to the drain of the fourth field effect transistor T₄, and agate connected to the gate of the seventh field effect transistor T₇.The eleventh field effect transistor T₁₁ comprises a source connected tothe gate of the fourth field effect transistor T₄, a drain connected tothe gate of the tenth field effect transistor T₁₀, and a gate connectedto the drain of the tenth field effect transistor T₁₀.

It is to be stated that the first and the fifth field effect transistorsT₁, T₅ each have a similar function as the first diode D₁ of the secondembodiment, and that the second and the sixth field effect transistorsT₂, T₆ each have a similar function as the second diode D₂ of the secondembodiment. The other field effect transistors (except for T₀) are infact an implementation for the voltages source V_(ls1), V_(ls2),etceteras.

What is claimed is:
 1. A level converter for the converting of a firstdigital signal (U₁) having a first voltage range into a second digitalsignal (U₂) having a second voltage range comprising an amplifier (T₀)having an input for receiving the first digital signal (U₁) and anoutput for supplying the second digital signal (U₂), a seriesarrangement for controlling the slew-rate of the second digital signal(U₂) which comprises at least a first capacitor (C₁) and a secondcapacitor (C₂) and which is coupled between the output and the input ofthe amplifier (T₀), and voltage controlling means for controlling thevoltages (V_(C1), V_(C2)) across the at least first and secondcapacitors (C₁, C₂), characterized in that the voltage controlling meanscomprises at least one voltage source (V_(ls1), V_(ls2)) for supplying aseparate bias voltage to each internal node (N₁, N₂) of the seriesarrangement, and in that the value of the separate bias voltage or thevalues of the separate bias voltages is/are dependent on the values ofthe first (U₁) and the second (U₂) digital signals.
 2. A level converteras claimed in claim 1, characterized in that a bias resistor (RB) isarranged in series with at least one of the at least one voltagessources (V_(ls1), V_(ls2)).
 3. A level converter as claimed in claim 1,characterized in that switching means is/are arranged in series with theat least one voltages sources (V_(ls1), V_(ls2)).
 4. A level converteras claimed in claim 3, characterized in that the switching means (D₁,D₂) is formed by diodes (D₁, D₂).
 5. A level converter for theconverting of a first digital signal (U₁) having a first voltage rangeinto a second digital signal (U₂) having a second voltage rangecomprising a transistor (T₀) having a control terminal (G), a first mainterminal (S), and a second main terminal (D), whereby the controlterminal (G) and the first main terminal (S) form together an input forreceiving the first digital signal (U₁), and whereby the second mainterminal (D) and the first main terminal (S) together form an output forsupplying the second digital signal (U₂), a series arrangement forcontrolling the slew-rate of the second digital signal (U₂) whichcomprises a first capacitor (C₁) and a second capacitor (C₂) and whichis coupled between the second main terminal (D) and the control terminal(G) of the transistor (T₀), and voltage controlling means forcontrolling the voltages (V_(C1), V_(C2)) across the first and secondcapacitors (C₁, C₂), characterized in that the voltage controlling meanscomprises a first voltage source (V_(ls1)), a first diode (D₁) arrangedin series with the first voltage source (V_(ls1)), a second voltagesource (V_(ls2)), and a second diode (D₂) arranged in series with thesecond voltage source (V_(ls2)), and in that the series arrangement ofthe first voltage source (V_(ls1)) with the first diode (D₁) is arrangedin parallel with the first capacitor (C₁), and in that the seriesarrangement of the second voltage source (V_(ls2)) with the second diode(D₂) is arranged in parallel with the first capacitor (C₁).
 6. A levelconverter for the converting of a first digital signal (U₁) having afirst voltage range into a second digital signal (U₂) having a secondvoltage range comprising a transistor (T₀) having a control terminal(G), a first main terminal (S) coupled to a supply reference terminal(GND), and a second main terminal (D), whereby the control terminal (G)and the supply reference terminal (GND) form together an input forreceiving the first digital signal (U₁), and whereby the second mainterminal (D) and the supply reference terminal (GND) together form anoutput for supplying the second digital signal (U₂), a seriesarrangement for controlling the slew-rate of the second digital signal(U₂) which comprises a first capacitor (C₁), a second capacitor (C₂),and a third capacitor (C₃), and which is coupled between the second mainterminal (D) and the control terminal (G) of the transistor (T₀), andvoltage controlling means for controlling the voltages (V_(C1), V_(C2),V_(C3)) across the first, the second and the third capacitors (C₁, C₂,C₃), characterized in that the voltage controlling means comprises firstuntil seventh field effect transistors (T₁-T₇) of a first conductiontype and eighth until eleventh field effect transistors (T₈-T₁₁) of asecond conduction type, and in that the first field effect transistor(T₁) comprises a first main terminal coupled to a common node (N₁) ofthe first capacitor (C₁) and the second capacitor (C₂), a second mainterminal coupled to the second main terminal (D) of the transistor (T₀),and a gate, and in that the second field effect transistor (T₂)comprises a first main terminal coupled to the gate of the first fieldeffect transistor (T₁), and a second main terminal and a gate which areboth coupled to the first main terminal of the first field effecttransistor (T₁), and in that the third field effect transistor (T₃)comprises a first main terminal, a second main terminal coupled to thesecond main terminal (D) of the transistor (T₀), and a gate, and in thatthe fourth field effect transistor (T₄) comprises a first main terminalcoupled to the gate of the first field effect transistor (T₁), a secondmain terminal coupled tot the first main terminal of the third fieldeffect transistor (T₃), and a gate, and in that the fifth field effecttransistor (T₅) comprises a first main terminal coupled to a common node(N₂) of the second capacitor (C₂) and the third capacitor (C₃), a secondmain terminal coupled to the first main terminal of the first fieldeffect transistor (T₁), and a gate, and in that the sixth field effecttransistor (T₆) comprises a first main terminal coupled to a biasreference terminal (BIAS) for receiving a bias voltage (V_(BIAS)), and asecond main terminal and a gate which are both coupled to the first mainterminal of the fifth transistor (T₅), and in that the seventh fieldeffect transistor (T₇) comprises a first main terminal coupled to thegate of the fifth field effect transistor (T₅), a second main terminalcoupled to the first main terminal of the fourth field effect transistor(T₄), and a gate coupled to the bias reference terminal (BIAS), and inthat the eighth field effect transistor (T₈) comprises a first mainterminal coupled to the gate of the third field effect transistor (T₃),a second main terminal coupled to the second main terminal of thetransistor (T₀), and a gate, and in that the ninth field effecttransistor (T₉) comprises a first main terminal coupled to the gate ofthe third field effect transistor (T₃), a second main terminal coupledto the gate of the eight field effect transistor (T₈), and a gatecoupled to the second main terminal of the transistor (T₀), and in thatthe tenth field effect transistor (T₁₀) comprises a first main terminalcoupled to the gate of the fourth field effect transistor (T₄) and tothe gate of the eight field effect transistor (T₈), a second mainterminal coupled to the second main terminal of the fourth field effecttransistor (T₄), and a gate coupled to the gate of the seventh fieldeffect transistor (T₇), and in that the eleventh field effect transistor(T₁₁) comprises a first main terminal coupled to the gate of the fourthfield effect transistor (T₄), a second main terminal coupled to the gateof the tenth field effect transistor (T₁₀), and a gate coupled to thesecond main terminal of the tenth field effect transistor (T₁₀).